FIG. 1A illustrates a conventional architecture of a line card, used in a network communication device that includes a link layer device and a framer. The link layer device typically includes components such as a network processor, a network co-processor, memory, data path switching element (DSE), network search engine (NSE), and a clock management block. The network processor and/or a framer usually performs packet processing functions. Packet processing functions may involve tasks such as packet pre-classification or classification, protocol conversion, quality of service assurance, service policing, provisioning, and subscriber management functions. The framer is used to transport data such as ATM (asynchronous-transfer-mode) cells, IP packets, and newer protocols, such as GFP (generic framing procedure) over SONET (synchronous optical network)/SDH (synchronous packet processing system hierarchy) links. On the port side, the framer may support optical-networking protocols for both SONET/SDH and direct data-over-fiber networks. The framer is coupled to the physical layer port such as a SONET device, which is coupled to a network medium such as optics. On the system side, the framer interfaces to the link-layer device usually through standard buses, for example, the Universal Test and Operation Physical interface device for ATM (UTOPIA) or Packet Over SONET-physical layer (POS-PHY) buses.
A packet processing function may also involve tasks such as error detection, and the cyclical redundancy check (CRC) algorithm is commonly used to implement this in communication systems. The CRC algorithm is among the strongest checksum algorithms available for detecting and correcting errors in communications packets. In a high-speed design as the system operating speed increases it is common design practice to expand the internal bus width. An exemplary 10 G (10 gigabits per second) system may have a 128-bit wide bus.
A conventional architecture for implementing the CRC protocol is shown in FIG. 1B. This architecture comprises N number of CRC calculators to process an N-byte wide bus. FIG. 1B shows an exemplary N byte wide input bus coupled to a plurality of byte-wide calculators comprising a first byte calculator, second byte calculator and so on up to an Nth byte calculator. The input data from the input bus is passed to all the CRC byte calculators in parallel. The output of the CRC calculators is passed to a multiplexer, and the output of the multiplexer (a CRC output taken from the selected CRC calculator) is chosen based on the byte-enable at the end of packet (EOP).
A disadvantage of this conventional implementation is that the number of fast and pipelined CRC calculators required equals the number of bytes in the bus-width. Fast and pipelined CRC calculators typically require significant die area and consume a significant amount of power during their operation. In this conventional implementation, as the input bus-width increases the area and power required by the implementation increases rapidly.